Experimenting with Design of Low Power Johnson Counter Using Lector Technique Using 50nm Technology

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Experimenting with Design of Low Power Johnson Counter Using Lector Technique Using 50nm Technology

October 16, 2020 Engineering 0

In the design of CMOS VLSI circuits, power dissipation is a significant concern. High power consumption, in the case of battery-powered applications, results in a decrease in battery life and affects the cost of durability, packaging and cooling. The scaling down of the threshold voltage levels in turn induces an exponential increase in sub threshold leakage currents, leading to an increase in leakage power, with technology processes progressing towards deep submicron and nano regimes. A five-fold increase in leakage power dissipation is present as each generation of the manufacturing process progresses. When the circuit is idle, leakage currents flow and so power is lost. For deep submicrons and nanometers, successful leakage power reduction techniques have become important.
Circuit loops. A 4-bit Johnson counter is designed using LECTOR technology in this paper and is analysed with various kinds of sleep techniques. For designing, we have used the digital schematic editor (DSCH); Micro wind Layout Editor is used for simulation and layout generation. In this paper, using various sleep methods and LECTOR techniques, the power consumption of the 4-bit Johnson counter is reduced. Unlike other leakage control techniques, no additional control circuitry is needed by LECTOR to track the circuit states.

Author (s) Details

Dr. A. Yasmine Begum
Department of Electrical and Electronics of Engineering, Sree Vidyanikethan Engineering College, A. Rangampet, Tirupati, India.

Mr. M. Balaji
Department Electronics and Communication Engineering, Sree Vidyanikethan Engineering College, A. Rangampet, Tirupati, India.

Dr. N. Padmaja
Department Electronics and Communication Engineering, Sree Vidyanikethan Engineering College, A. Rangampet, Tirupati, India.

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