Experimenting with Design of Low Power Johnson Counter Using Lector Technique Using 50nm Technology

In the design of CMOS VLSI circuits, power dissipation is a significant concern. High power consumption, in the case of battery-powered applications, results in a decrease in battery life and affects the cost of durability, packaging and cooling. The scaling down of the threshold voltage levels in turn induces an exponential increase in sub threshold…
Read more

October 16, 2020 0